We are looking for an experienced RTL Design Engineer to join our SoC/ASIC design team. The ideal candidate will have strong expertise in micro-architecture, RTL coding, and complex digital design for high-performance chips.
Define and develop micro-architecture for digital IP blocks and subsystems.
Write high-quality RTL code using Verilog/SystemVerilog.
Perform functional modeling, design optimization, and implementation.
Collaborate with DV, PD, and architecture teams to ensure seamless integration.
Conduct lint, CDC, RDC, synthesis checks and resolve issues.
Participate in design reviews, documentation, and signoff processes.
Work closely with verification teams to ensure 100% functional correctness.
7+ years of hands-on experience in RTL Design for ASIC/SoC.
Strong knowledge of Verilog/SystemVerilog.
Experience in micro-architecture definition and design specifications.
Solid understanding of Digital Design fundamentals (timing, power, reset, clocking).
Good exposure to Synthesis, STA, Lint, CDC/RDC tools.
Experience working with AMBA protocols (AXI/AHB/APB) or high-speed interfaces.
Ability to debug complex design and verification issues.
Strong communication and documentation skills.
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