We are looking for skilled RTL Design Engineers to join our semiconductor design team. The role focuses on developing high-quality RTL for complex SoC/IP blocks, ensuring functional correctness, performance, and power efficiency while working closely with verification, architecture, and physical design teams.
Develop RTL designs for SoC/IP modules using Verilog/SystemVerilog.
Translate architectural specifications into clean, optimized, synthesizable RTL.
Collaborate with architects to define micro-architecture and design specifications.
Work closely with verification teams to review test plans, support testbench bring-up, and debug functional issues.
Perform CDC, Lint, Timing (STA) reviews, and RTL-level optimizations.
Handle synthesis constraints, debug synthesis/DFT issues, and drive design closure.
Participate in design reviews, documentation, and design sign-off activities.
Work with cross-functional teams (DV, PD, DFT, FW) throughout the design cycle.
Strong experience in RTL design using Verilog/SystemVerilog.
Solid understanding of digital design fundamentals, logic design, and micro-architecture.
Hands-on knowledge of synthesis, timing constraints, and RTL optimization.
Experience with tools such as Synopsys DC, VCS, Spyglass Lint, Verdi, or equivalent.
Good understanding of AMBA protocols (AXI/AHB/APB) and other standard interfaces.
Exposure to low-power design techniques (UPF/CPF) is an advantage.
Familiarity with DFT concepts, clock/reset architectures, and CDC analysis.
Strong problem-solving skills and ability to debug complex RTL or integration issues.
Ability to work collaboratively in fast-paced semiconductor development environments.
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