We are looking for experienced Design-for-Test (DFT) Engineers with strong hands-on expertise in Tessent tools and digital test methodologies. The ideal candidate should be capable of working independently, driving DFT activities across the design cycle, and collaborating effectively with cross-functional teams.
Perform Tessent DFT RTL insertion, execute DRC checks, and resolve DFT-related issues.
Implement and validate Scan Insertion, ATPG, and MBIST structures.
Conduct Gate-Level Simulations (GLS) including timing-enabled GLS and debug failures efficiently.
Generate and verify MBIST patterns, ensuring robust memory test coverage.
Work with DFT IPs such as OCC, EDT, SSN, MBIST controllers, IJTAG, and boundary scan architectures.
Communicate debug findings and DFT issues clearly with the broader design and verification teams.
Manage tasks independently and ensure timely delivery of all DFT deliverables.
5+ years / 10+ years of hands-on DFT experience.
Strong practical knowledge of Mentor Tessent DFT tool flows.
In-depth understanding of scan, ATPG, MBIST, and GLS methodologies.
Familiarity with IEEE 1500/1600 standards, boundary scan design, and IJTAG.
Solid debugging and problem-solving skills.
Working knowledge of TCL scripting is a plus.
Ability to work independently and collaborate within a fast-paced engineering environment.
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